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IC Chip
Materials Analysis
Atomic imaging, elemental analysis, lattice spacing, depth profiling, void identification, void distribution along film depth, and crystalline structure

Reliability Testing
Test Performed
Electrical
Thermal
Optical
Lifetime Prediction
Environmental
Altitude
Mechanical

Test Standards
JEDEC, MilStd and Tecordia

HTOL       HALT       HASS
Failure Analysis
Typical Failure Mode
Short, open, ESD, EOS, leakage, and package broken

Failure Analysis Tools
SEM
OBIRCH
X-ray
FIB
Decap/X-section/P-lap

Reverse Engineering
Test Performed
Block identification, chip/pad dimensions, IO pads, technology node, memory block size, memory type, metal structure and material, package layer, bump-pitch/pad, pin connection configuration and mapping, solder ball/pad, ubm size, and Via

Decapsulation
Delayering
Polishing
Ion-Milling
Key Technology #1
ISO 9001: 2018
  • System architecture design, planning for production, operation, services, and decommissioning
  • Process can be characterized, tested, and analyzed from a safety perspective
  • FMEA, FTA, and bath tub analysis
  • FIT and failure rate estimation/calculation, and failure mode distribution (diagnostic capabilities)
  • Hardware component test plan
  • Qualification plan and report
Key Technology #2
High Accelerated Life Test (HALT)
High Accelerated Stress Screen (HASS)

HALT: Defines the upper spec limit (USL) and lower spec limit (LSL) to build profile
HASS: Ensures the outputs between USL and LSL

With continuously shrinking technology nodes, IC chip industry depends more and more on high resolution TEM/EDS/EELS technology. Outermost Technology has provided its high-quality analysis to leading Silicon Valley companies from various industries including semiconductor materials, IC chip failure analysis, and reverse engineering.
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