The Device Testing business unit is comprised of Reliability Testing (RT) and Failure Analysis (FA) Services. Reliability Testing involves testing the lifetime, environmental, electrical, thermal, and mechanical durability of a device to ensure it meets the expected lifetime. Failure Analysis can be used to identify the root cause of failure in a device
Reliability is defined as the ability of a device to conform to its electrical and visual/mechanical specifications over a specified period of time under specified conditions at a specified confidence level. Reliability engineering employs a wide variety of reliability tests like the lifetime, environmental including humidity, electrical, thermal, mechanical testing. RT is often divided into the wafer level RT and package level RT, too. Wafer-level RT is when the first silicon comes out to check the reliability issue at the early stage. Package level RT uses one or more of the following stress factors to accelerate failure: temperature, moisture or humidity, current, voltage, and pressure. The most popular industry-standard reliability tests for semiconductors are already available. Outermost Technology provides the testing services for your chips' reliability and provides the engineering consulting for failure analysis and design for reliability.
| Tested Environmental Conditions | |||
|---|---|---|---|
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| Mechanical Test | Conditions |
|---|---|
| Mechanical Shock | 340 g - 10,000 g; 5 shocks per orientation; JESD22-B110B |
| Vibration & Resonance | 20 Hz - 2000 Hz, 4 cycles for 3 axis; 12 cycles total; JESD22-B103B |
| Universal Testing Machine | Shear, pull, edge break, body strength, 3 points bending tests |
| Bending | Speed: 20 mm/min; JESD22-B113 |
| Torsion & Free Drop | 1 Hz/25 times & 1.0 mm/min speed |
| HALT | Optional temperature & vibrational stressing, IPC9592A |
| Lifetime Test | Conditions |
|---|---|
| Early Life Failure Rate | T ≥ 125°C; 48 hrs ≤ t ≤ 168 hrs; ELFR-JEDEC/ELFR-AEC-Q100-008 |
| HTOL | 125°C; 1008 hrs; other conditions available; JESD22-A108 |
| LTOL | -65°C; 1008 hrs; other conditions available; JESD22-A108 |
| Erase and Write | 125°C;168 hrs; other conditions available; JESD22-A117/AEC-A100-005 |
| PLT | 25°C; 1008 hrs; other conditions available; JESD22-A108 |
| Environmental Test | Conditions |
|---|---|
| Temperature Cycling | -65°C to +150°C; other conditions available; TC-JEDEC/TS-Mil-Std-883 |
| Thermal Shock | -65°C to 150°C; JESD22-A106/Mil-Std-883, method 1011 |
| THB | 85°C, 85% RH, 1000 hrs; other conditions available; JESD22-A101 |
| HTS | +85°C to +300°C; JESD22-A103/Mil Std 883, method 1008 |
| LTS | -65°C to -40°C; JESD22-A119/EIAJ ED-4701/200, test method 202 |
| HAST | 130°C, 85% RH, 96 hrs; other conditions available; JESD22-A110 |
| Pressure Cooker Test | 121°C, 100% RH, 96 hrs; other condittions available; JESD22-A102 |
| Salt Atmosphere Test | [Salt]: 0.5% to 3%; JESD22-A107/Mil-Std883, method 2005 |
| Preconditioning of SMD | Prior to THB, HAST, TC, AC, and UHST; JESD22-A113/JSTD-020 |
| Moisture Sensitivity Level | Level 1 to 6; JSTD-020 |
| Reliability Services | Description |
|---|---|
| Design for Excellence (DFX) | Advanced design for analysis, debug, manufacturing, reliability, test, service |
| Failure in Time (FIT) | Failure rate that occurs during one billion device hours |
| Failure Mode and Effects Analysis (FMEA) | Evaluate failure occurrence, detectability, severity and consequences |
| Acceleration Factor, Temperature (AT) | Calculated from activation energy, Boltzmann constant, stress T, failure rates |
| Mean Time Between Failure (MTBF) | Predicted from bill of materials (BOM), stress analysis and AT |
| TeraBytes Written (TBW) | Estimate the total amount of data that can be written to the NAND device in its lifetime |
Eventually, every chip is going to fail or fall short of desired functionality. Understanding the root causes behind these failures can improve your products to stand out amongst competitors or reveal a clue of the more significant potential problems lurking below the surface.
Outermost Technology has extensive semiconductor failure analysis capability from the initial non-destructive level 1 analysis, level 2 optical fail localization using PHEMOS/THEMOS, and level 3 advanced fail spot analysis like TEM/EELS, AFM/SCM/SSRM/C-AFM, micro-probing of the failed spot/bits.
| Level | Analysis Process | Analysis Equipment |
|---|---|---|
| Level 1 | External Inspection | Low/High Power Scope |
| Electrical Test | Pin or Wafer Level Electrical Testing | |
| Non-Destructive Analysis | Regular X-ray Imaging | |
| 3-D X-ray Imaging | ||
| Confocal Scanning Acoustic Microscope (C-SAM) | ||
| Decapsulation | Chemical/Mechanical Method | |
| Level 2 | Optical Fall Localization | Photon Emission Microscopic Analysis (PHEMOS) & Thermal Emission Microscopic Analysis (THEMOS) |
| Optical Beam Induced Resistance Change (OBIRCH) | ||
| Backside IR Imaging | ||
| Liquid Crystal Analysis | ||
| Level 3 | Fall Root Cause Imaging | Focused Ion Beam (FIB) Cross Section |
| Scanning Electron Microscope (SEM) | ||
| Transmission Electron Microscope (TEM) & EDS/EELS | ||
| Advanced Failure Spot Analysis | Energy Dispersive X-ray Spectroscopy (EDS) & Electron Energy Loss Spectroscopy (EELS) |
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| Atomic Force Microscopy (AFM) & Scanning Capacitance Microscopy (SCM) & Scanning Spread Resistance Microscopy (SSRM) |
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| Micro-Probing of the Failed Spot/Bits |
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